This application claims the benefit of Korean Patent Application No. 97-48370, filed Sep. 24, 1997, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a fabrication method of a thin film transistor (TFT) for a liquid crystal display (LCD), and more particularly, to a TFT that draws less leakage current.
2. Discussion of the Related Art
A basic unit of an LCD includes a switching device (TFT) that drives a pixel having a pixel electrode. The TFTs and the pixels are arrayed in a matrix. The TFT includes a gate, a source and a drain. The gate is formed in an active region that includes polycrystalline silicon or amorphous silicon. TFTs are classified into two types: a top gate type and a bottom gate type, where the top gate type has a gate in an upper part of the active region, and the bottom gate type has a gate in a lower part of the active region.
Depending on a shape of the gate, TFTs are classified into a standard type and a dual gate type. The TFTs are also classified into a lightly doped drain (LDD) type and an offset type depending on the relative locations of a source region, a drain region and a gate region.
TFTs of the LDD type and the offset type reduce the leakage current because they have an active layer made of polycrystalline silicon and a structure where the source, the drain and the gate do not overlap. The LDD-type TFT has a region doped lightly with impurities between a source/drain region and the gate in the active layer, while the offset-type TFT does not have such a corresponding doped region.
FIGS. 1A to 1D show a conventional fabricating method of the TFT. Referring to FIG. 1A, an active layer 13 is formed by patterning a silicon layer using photolithography. The silicon layer has been deposited on a substrate 11 and includes undoped amorphous silicon or polycrystalline silicon. A gate insulating layer 15 is formed by depositing silicon oxide to cover the active layer 13.
Referring to FIG. 1B, a gate 17 is formed by patterning an aluminum layer that has been deposited on the gate insulating layer 15 using photolithography, where a portion of the aluminum layer remains over a center portion of the active layer 13. A lightly doped region 19 making up an LDD structure is formed by lightly doping with N-type impurities a region that does not overlap the active layer 13, with the gate 17 being used as a mask. The undoped portion of the active region 13 under the gate 17 becomes a channel region of the TFT. When an offset type TFT is formed, the active layer 13 is not doped with impurities.
Referring to FIG. 1C, side walls 21 are formed at sides of the gate 17 by etching back a silicon oxide layer which has been deposited to cover the gate on the gate insulating layer 15. Using the gate 17 and the side walls 21 as a mask, a heavily doped region 23 used as source and drain regions is formed by doping it heavily with N-type impurities. If the lightly doped region 19 is not formed, the region 19 between the gate 17 and the heavily doped region 23 becomes an offset region.
Referring to FIG. 1D, an insulating interlayer 25 is formed by depositing silicon oxide to cover the gate 17 and the side walls 21 on the gate insulating layer 15. Contact holes 27 are formed by patterning the insulating interlayer 25 using photolithography to expose the heavily doped region 23. A source electrode 28 and a drain electrode 29 are formed in contact with the heavily doped region 23.
FIG. 2 shows a cross-sectional view of additional steps in the fabrication of the TFT.
After the steps shown in FIGS. 1A to 1B have been carried out, a heavily doped region 23 for use as source and drain regions is formed by heavily doping it with N-type impurities and using a mask 22 covering an area bigger than the top surface of the gate 17, which is located in the center. The width of the lightly doped region 19 between the gate 17 and the highly doped region 23 depends on the width of the mask 22 as shown in FIG. 2. Then the steps shown in FIG. 1D are performed.
In the conventional fabricating method of the TFT, the length of the lightly doped region and the length of the offset region should be limited to no more than 2 xcexcm. Accordingly, the process becomes complicated due to an added step of forming sidewalls to define the lightly doped region and the offset region. Also, defining the width of the side walls 21 to more than or equal to 2 xcexcm is difficult.
In addition, the process gets more complicated when the lightly doped region or the offset region is defined by aligning a mask.
Accordingly, the present invention is directed to a fabrication method of a thin film transistor (TFT) for a liquid crystal display (LCD) that substantially obviates one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present inventions to provide a simple process for defining a lightly doped region or an offset region without using a mask or side walls.
Additional features and advantages of the present invention will be set forth in the description which follows, and will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and process particularly pointed out in the written description as well as in the appended claims.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in a first aspect of the present invention there is provided a method of fabricating a thin film transistor including the steps of forming an active layer on a substrate, forming a gate insulating layer covering the active layer and the substrate, forming a gate on a portion of the gate insulating layer and over the active layer, forming an insulating interlayer on the gate insulating layer to cover the gate, forming contact holes exposing a portion of the active layer by patterning the insulating interlayer and the gate insulating layer, and forming a heavily doped region by heavily doping the portion of the active layer exposed by the contact holes.
In another aspect of the present invention there is provided a method of fabricating a thin film transistor including the steps of forming an active layer on a substrate, forming a gate insulating layer on the substrate and the active layer, forming a gate on a portion of the gate insulating layer and over the active layer, forming a lightly doped region by ion implantation of N-type impurities or P-type impurities and using the gate as a mask, forming an insulating interlayer on the gate insulating layer and covering the gate, forming contact holes to expose portions of the active layer by patterning the insulating interlayer and the gate insulating layer, and forming a heavily doped region by heavily doping the portions of the active layer exposed by the contact holes with the same impurities as the lightly doped region.
In another aspect of the present invention there is provided a method of fabricating a thin film transistor including the steps of forming a gate on a first area of a substrate, forming a gate insulating layer over the substrate and covering the gate, forming an active layer on the gate insulating layer covering the first area corresponding to the gate, forming an insulating interlayer on the gate insulating layer and covering the active layer, forming contact holes to expose second areas on the active layer by patterning the insulating interlayer, forming a highly doped region by highly doping the second areas.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.